Industry Applications

Chip detection

Block-by-block test planning for SoC devices must be implemented: correctly configured ATPG tools for logic testing; short test times; new high-speed failure models; and multiple memory or small array tests. For the production line, the diagnostic method is not only to find the fault, but also to separate the fault node from the working node. In addition, whenever possible, test reuse techniques should be used to save test time. In the field of highly integrated IC testing, ATPG and IDDQ's design for testability technology has a strong fault isolation mechanism.
Other practical parameters that need to be planned in advance include the number of pins to be scanned and the amount of memory at each pin end. Boundary scan can be embedded on the SoC, but is not limited to interconnect testing on a circuit board or multi-chip module.
Although the chip size is decreasing, a chip can still pack millions to 0.1 billion transistors, and the number of test modes has increased to an unprecedented level, resulting in a longer test cycle. This problem can be solved by compressing the test modes, with a compression ratio of 20% to 60%. For the current large-scale chip design, in order to avoid capacity problems, it is necessary to find test software that can run on 64-bit operating systems.